Synch verilog-mode.el to latest upstream version.
authorWilson Snyder <wsnyder@wsnyder.org>
Wed, 26 Sep 2012 03:32:51 +0000 (11:32 +0800)
committerChong Yidong <cyd@gnu.org>
Wed, 26 Sep 2012 03:32:51 +0000 (11:32 +0800)
commit0ac72c784316736c59f0113cfa71e0a0221f2db6
treeb0e03c65cf537254d664963eb68d67ab36155d74
parent951b960d37c95fcdfac26084324ec0aa923fab08
Synch verilog-mode.el to latest upstream version.

* verilog-mode.el (verilog-auto-ascii-enum, verilog-auto-inout)
(verilog-auto-input, verilog-auto-insert-lisp)
(verilog-auto-output, verilog-auto-output-every, verilog-auto-reg)
(verilog-auto-reg-input, verilog-auto-tieoff, verilog-auto-undef)
(verilog-auto-unused, verilog-auto-wire)
(verilog-forward-or-insert-line): Fix AUTOs with no trailing
newline.  Reported by Andrew Jones.
(verilog-auto-inst) Support expanding $clog2 in AUTOINST.
Reported by Brad Dobbie.
(verilog-batch-delete-trailing-whitespace): Create
verilog-batch-delete-trailing-whitespace.  Reported by Brad
Dobbie.
(verilog-auto-inout-param): Support AUTOINOUTPARAM for copying
parameters from another module.  Reported by Dan Katz.
(verilog-auto, verilog-auto-assign-modport)
(verilog-auto-inout-modport): Add AUTOASSIGNMODPORT and
AUTOINOUTMODPORT for UVM interface module shell generation.
Reported by Brad Dobbie.
(verilog-auto-inst-interfaced-ports): Make default nil, as more
standard behavior.
(verilog-auto): Fix AUTO parameters with parenthesis arguments.
Reported by Matt Martin.
lisp/ChangeLog
lisp/progmodes/verilog-mode.el